Insights from NAFEMS World Congress

June 17, 2013 | By Benzi Galili

The NAFEMS World Congress took place in Salzburg last week.

This event included many great presentations by engineers running simulations in different fields, by the ISVs showcasing their latest developments and enhancements, and by academic researchers.

ScaleMP’s presentation (and paper submission) was focused on usage of large memory for FEA, with very large models running out-of-core, where the user can get up to 5x speed up compared to the fastest IO devices if they run in-core (e.g. using vSMP Foundation for Memory Expansion to create very large memory on-top of the standard x86 cluster), and the ROI of this add-on enhancement to the infrastructure.

A few themes were strongly underscored and were worth noting (in addition to ScaleMP’s booth presence and paper assertion/presentation).

  • More and more solvers are highly optimized for use with MPI clusters. Many solvers that did not previously scale well are now significantly improved, from all of the major vendors.
  • GPGPUs/Co-processors are a fact of life for simulations/computing with CAE. It no longer is a question of will it be there for FEA, it is now a question of how fast the users will adopt this next wave. The gains are not as spectacular as with other scientific/simulations domains, and it appears like the consensus is roughly a 2x speedup vs. an x86 socket, but given the very generous licensing models offered by the ISVs (some officially talking about a full GPGPU license costing as little as a single x86 core token), it seems like the end-users are being made an offer they can’t refuse.
  • Engineering data management is becoming a key factor, and the discipline is being noticed and promoted. To me, that speaks about maturity: it is not just about the simulation also the lifecycle – the enormous amounts of data being generated must not only be saved, but actually tapped into to get more value out of it.
  • The sophisticated users are pushing for simulation much earlier in the design cycle, including the conceptual design phases. This enables them to further cut costs, speed up the development and shorten time to market, and also have grater trust in the final results built into the process early on.

I was also happy to see that the HPC community is taking part in this professional event via the HPC track in the breakout sessions. There were excellent presentations, there was good attendance, and I hope that the community aspect of this sub organization (the HPC Working Group) would attract even more interest and participation. HPC is turning CAE and engineering simulation into a strategic advantage.